An Overview: RF Design of Fast Locking Digital Phase Locked Loop

Phase locked loop (PLL) is a control system that generates a signal having a fixed relation with the phase of a reference signal. This system responds to both frequency and phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. The performance of PLL is primarily dependent on the lock time, it is the time PLL takes to adapt and settle after a sudden change of the input signal frequency. It is desired to design a novel fast locking digital PLL. The high speed, high throughput applications needed for information technology demand that the lock time should be as small as possible. Fast locking is also of great importance for fast frequency hopping among data bursts in high-speed digital communications. Various technologies used for the improvement of the PLL design, to make it work faster are discussed in this paper. Keywords— Phase Locked Loop (PLL), Injection Locked Frequency Divider (ILFD), Radiation Hardened Design Topology (RHDT), Single Event Transient(SET).